In Reference Flow 12.0, Apache’s power, thermal and stress analysis products enable validation for TSMC’s 3D-IC/Silicon Interposer architectures. The AMS Reference Flow 2.0, targeted at 28 nm process technology, includes Apache’s Totem platform for power and noise analysis.
"Power, noise and thermal impacts are major concerns for advanced designs using Silicon Interposer and TSV structures," said Suk Lee, director of design infrastructure marketing at TSMC. "Noise margin reduction and thermal induced stress can cause chip failures, and including Apache’s products in TSMC’s Reference Flows and the industry’s most complete 28nm design infrastructure helps enable customers to better manage their power and noise challenges to ensure silicon success."
The demand for low-power, high-performance, and cost-effective products is driving the need for multi-die technologies such as 3D-IC. These advanced technologies need to combine several heterogeneous die representing both digital and analog functions using varying process nodes in a single package connected through Silicon Interposer with TSV. However, the use of these technologies pose major power, thermal, and stress challenges due to the coupling of power/ground noise and heat transfer between the die, silicon substrate, package, and board. Apache’s RedHawk, Totem, and Sentinel help provide accurate power, noise and thermal analysis of a multi-die design using both concurrent and model-based methodologies.
The model-based approach accounts for IP protection of various die. The CPM generated by RedHawk and Totem contains power behavior of the die in a compact, portable format. These models can be used in conjunction with the layout data to analyze power integrity for the entire chip. The concurrent simulation method provides the highest degree of accuracy, especially as the number of shared power/ground networks increases. Both approaches include package parasitics in their analysis for a complete view of the Chip-Package-System (CPS).
Overheating and thermal induced stress are major challenges for 3D-IC and Silicon Interposer designs. Apache’s CTM provides an accurate, geometry aware, layer-by-layer power distribution model of the die for thermal and thermal-induced stress analysis. Sentinel utilizes CTM to analyze the thermal and stress behavior of the chip-package-board assembly to mitigate the risk of system failure.
At the 28nm node, greater transient current due to higher transistor density poses major power and reliability challenges for analog and mixed signal designs, requiring an accurate transistor-level sign-off solution with full-chip capacity. The manual implementation nature of the analog design significantly increases the chip failure risk caused by power noise. In TSMC’s Reference Flow 2.0, Apache’s Totem provides layout-based power analysis for analog and mixed-signal designs. It addresses the challenges associated with global couplings of power/ground noise, and package/PCB capacitive and inductive noise. Totem enables early feedback of IR and EM issues during layout stage to avoid costly iterative repairs and demonstrates the ability to perform power analysis in AMS designs.
Apache is showcasing the company’s products in the TSMC Reference Flows at the Design Automation Conference held at the San Diego Convention Center, June 6 to June 8, 2011, in booth #2448.
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