Diodes has launched a PCIe 3.0 packet switch with low power for data centre, cloud computing, network-attached storage (NAS), and telecom infrastructure designs.
The PI7C9X3G808GP packet switch supports 8-lane operation, accommodating 2-port, 3-port, 4-port, 5-port, and 8-port configurations. Cut-through, store and forward modes can be utilized with a packet forwarding latency of less than 150ns (typical) being supported.
The proprietary architecture employed in the switch provides multiple PCIe port / lane width combinations are available, as well as cross-domain end-point (CDEP) arrangements. With its CDEP capabilities, the chip supports fan-out and dual-host connectivity.
The built-in PCIe 3.0 clock buffer allows for a reduction in the overall component count and helps to curb BOM costs. This integrated buffer is unique to the industry, because of its low-power operation. Three different reference clock options can be used: common, separate reference no spread (SRNS), and separate reference independent spread (SRIS). Multiple direct memory access (DMA) channels have been embedded into the switch, in order to make communication between host (or hosts) and connected end-points as efficient as possible. It also includes error-handling, advanced error reporting, and end-to-end data protection with error correction.
The power management in the chip allows the switch to be used with hot-pluggable ports that are kept in a low-power state until needed. Under full load conditions and 80°C junction temperature, the PI7C9X3G808GP draws 2.9W of power.
The PI7C9X3G808GP is supplied in a high-performance flip-chip package, with 196-ball BGA format. It has dimensions of 15mm x 15mm. This next generation packet switch has a unit price of $20.13 in 1000 piece quantities.
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