Footprint-compatibility in these DC/DC units provides increased flexibility in power system design. The two added modules offer high performance without compromising on dynamic response; the auto-compensated digital POL regulators are based on ‘state-space’ or ‘model-predictive’ control, reducing cost and time-to-market while increasing flexibility
These modules also have Dynamic Loop Compensation (DLC), advanced energy-optimisation algorithms to reduce energy consumption, low-bias current technology, and a land-grid-array (LGA) footprint that guarantees excellent thermal, mechanical and electrical performance.
A feature of the two new modules is that they are 100% footprint compatible with the existing 12A BMR4613001 product; three different output currents – 6A, 12A and 18A – are available while only having to handle a single module footprint in new systems. This simplifies board design and makes it easier for power architects to move to higher or lower current-handling power modules without needing to redesign the system board when upgrading to new microprocessors or other advanced logic devices such as FPGAs or ASICs.
The BMR4614001 module is optimised to deliver 18A at 1.8V, making it suitable for processors operating at sub-2V core voltages. It is the first product of its kind to deliver this level of output current in a 12 x12mm footprint, while also delivering automatic loop compensation and full PMBus command capability.
The Dynamic Loop Compensation integrated into the 6A BMR4612001 and 18A BMR4614001 is based on “state-space” or “model-predictive” control, which guarantees stability while also achieving the optimum dynamic performance without requiring any external components. The new products perform an automatic compensation routine based on measured parameters, which enables the construction of an internal mathematical model of the power supply including external components such as filtering and parasitic resistors. Based on the ‘state-space’ mathematical model rather than traditional proportional-integral-derivative (PID) regulation, the devices use closed-loop pole placement and a model based on the resonant frequency of the output filter, thereby reducing the number of output capacitors required for filtering and stability. This technology is suitable for FPGA and processor applications where low-ESR decoupling capacitors are used currently.
The DLC is designed to accommodate the vast majority of applications via PMBus commands. Board-power designers can therefore tailor the loop compensation; for example, in low-output voltages to enhance the recovery time at load release by enabling a negative duty-cycle using the LOOP_CONFIG PMBus command. Many other parameters can be simply adjusted and monitored without any hardware modifications.
The new modules feature several algorithms that optimise efficiency across a wide range of operating conditions. Compared to the conventional technology that is currently implemented in analogue and digital-hybrid POL regulators, this combination of energy optimisation algorithms and low bias technology requires up to five-times less current, and therefore further improves overall efficiency. Because of this combination, significant gains in efficiency can be made, especially in sub-1V modules where it performs up 10 points higher than high-market-average units. For example, taking power from a 5V intermediate bus, the BMR461 modules power 0.6V applications at up to 85.7% efficiency at full load, whereas conventional units that are not using low-bias-current technology will have a typical efficiency of 75%. Or when operated from the 12V intermediate bus with the output set to 5V at 80% load, the modules deliver a typical efficiency of 96%.
BMR461 modules recognise 84 PMBus commands and include a non-volatile memory allowing board-power-designers to upload their own configuration files. Synchronisation is achieved through automatic pin detection and without the need for reconfiguration. In systems that use multiple BMR461s, the devices offer the ability to reduce EMI and the amount of input filtering through phase spreading via the PMBus INTERLEAVE command.
All three modules in the BMR461 family operate over 4.5V to 14.0V,which makes the products suitable for the most common bus voltages in intermediate-bus architecture systems, such as 5, 8 and 12V, and therefore reduces the number of modules required to carried in inventories. The output voltage can be adjusted from 0.6V to 5.0V by a strap-resistor or via the VOUT_COMMAND PMBus command.
The footprint is based on a matrix Land Grid Array (LGA) composed of 32 solder pads and has been developed to meet OEM manufacturing requirements in terms of pick-and-place, solderability and co-planarity, or future evolutions such as high power devices with 12×12 footprints, as well as additional features that require more interface pads. The use of LGA technology guarantees that each solder-pad will have an equal mass of solder providing excellent co-planarity. In addition, to reduce power losses each output is connected to six pads and the input uses four pads.
Overall dimensions of the modules are 12.2 x 12.2 mm with a maximum height of 8.0 mm making them suitable for use in low-board-pitch applications. The BMR461 family has an MTBF of 24 million hours. Other features include: pre-bias start-up and shut-down; monotonic and soft-start power-up; input under-voltage shutdown; over-temperature protection and power-good; output short-circuit and over-voltage protection; remote control and differential sense; voltage setting via pin-strap or PMBus; and an advanced set of configurations via the Ericsson DC/DC Digital Power Designer software.
Ericsson Power Modules; www.ericsson.com/powermodules