The SoC is designed to target entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. With the Cadence solution, UMC reduced the time to tapeout by 33 percent compared with the foundry’s previous solution and achieved performance of 1.7 GHz. In addition, UMC achieved a dynamic power consumption of less than 200 mW, which is a 20 percent reduction compared with the previous flow.
Using the multi-threaded Encounter Digital Implementation System, which incorporates GigaOpt route-driven optimization along with CCOpt concurrent clock datapath optimization, resulted in faster turnaround time with improved performance, die area and dynamic power. In addition, the seamless integration of Cadence Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Quantus QRC Extraction Solution, Physical Verification System, Litho Physical Analyzer and CMP Predictor allowed UMC to perform signoff checks much earlier in the process to affirm that the design functioned as intended upon completion.
“The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation and closure so we could quickly
deliver a quality reference design to market that exceeded our power, performance and area expectations,” said Shih Chin Lin, senior division director of IP Development and Design Support division at UMC.
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