Redesigned FPGA fabrics solve tough mid-range challenges: Page 3 of 4

October 23, 2018 //By Ted Marena
Redesigned FPGA fabrics solve tough mid-range challenges
New cost, power, and performance demands on FPGAs in a growing variety of mainstream, mid-range systems applications have led to fundamental changes in their design. Most FPGA vendors tend to focus on data-center workload applications, but a large percentage of users require different architectures for mainstream applications.

Flip-flops also must be designed to minimize clock power. To do this, clock gating is provided at two levels in the clock tree, as well as for each individual flip-flop, to avoid wasting power on unused branches. This can reduce clock power to less than half that of alternative 28-nm FPGAs, averaged over a suite of designs (as shown in Figure 3, which uses the PolarFire FPGA as an example of the new fabric approach).

The choice of operating voltage is also important. A power-performance trade-off must be carefully optimized for a 1.0-V core logic supply. In the case of FPGAs fabricated with SONOS NV technology on a 28-nm node, this is somewhat less than the 1.05-V nominal voltage for the process on which it’s manufactured. Customers desiring extra speed still have the option to use the full 1.05 V supply.

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