By combining implemented logarithmic current feedback and transient peak limiting circuits with the introduction of the parallel high speed amplification at fast varying load condition in main error amplifier (EA) great load transient and power supply rejection ratio (PSRR) can be achieved with excellent stability upon the entire load current range.
The design has been performed in 0.18 µm technology using special techniques in order to guarantee sub-1V operation of this LDO. The LDO is suitable for use in low power application with fast varying loads such as power supplies in portable electronic devices.
LDOs have become one of the most widespread power converters in portable electronics. As the integrated circuits (ICs), especially digital ones, keep increasing the number of transistors per square according to Moore's law and thus reducing the size of single components, new challenges arise for both LDOs and supply circuits as a whole.
Modern digital circuits require the power supply to be effective (eg low power consumption), have good load transient due to fast varying digital signals, and be able to work at low voltage levels providing stable outputs well under 1 V as with the decreasing component sizes their working voltage domains decrease as well.
As for analog and mixed signal circuits such as ADCs, lighting and sensor circuits, apart from the requirements mentioned above PSRR and noise performance become critical parameters for the supplies.
Several techniques exist for improving load transient performance of LDOs. This includes AB class output stage error amplifier (EA) for driving pass device's gate capacitance [Ref 1], adding a source follower as a buffer between amplifier and pass transistor [Ref 2], inclusion of an additional current amplifier in a feedback loop to accelerate reaction of LDO [Ref 3].
There is also a variety of possibilities to make LDO capable to work in a sub 1V domain ranging from integration of a digital controlled loop as in [Ref 4] to