Power gallium-nitride ( GaN) devices are an exciting addition to the power designer’s tool box. This is true specifically where there is a desire to explore how GaN’s higher switching frequencies can lead to higher efficiencies and higher power densities. RF GaN is a proven technology in high-volume production for power amplifiers used in cellular base stations and several military/aerospace systems due to its advantages over silicon.
Power GaN has lagged RF GaN because of the time required to implement cost-reduction strategies used by multiple suppliers. Most notably is the move to 6-inch silicon substrates and lower cost plastic packaging. It is important for power designers to understand performance improvement promises of GaN, as well as some of the degradation mechanisms that can affect the performance of the final product over time.
Joint Electron Device Engineering Council (JEDEC) qualification standards for silicon have proven to be good predictors for product lifetimes, but there is no equivalent standard for GaN today. To mitigate the risk of using new technologies, it is prudent to look at the specific-use case and environmental limits where the new technology is to be applied and build up prototypes that can be stressed and monitored for change. Real-time monitoring of a large number of prototypes poses some interesting engineering challenges, especially when GaN device voltages can approach 1000V and have dv/dts greater than 200 V/ns.
One commonly used graph to determine whether a power FET can meet the intended use case is the safe operation area (SOA) curve. One example is shown in Figure 1.
Figure 1. Example of a GaN FET SOA curve with Rds-On = 100 milliohm
Power GaN FETs are used in both hard-switched and multi-megahertz resonant designs. Either zero-voltage (ZVS) or zero-current (ZCS) topologies are being demonstrated above several kilowatts. The most stressed region of the SOA curve is at