High-performance processors demand subvolt power rails that can rapidly source and sink current. It is a testing challenge to duplicate these large current swings to verify power supply performance. The two main challenges are to minimize the load inductance in the test setup and to make the proper voltage measurement.
Inductance in your test setup is a problem, but when combined with low voltage and rapid current transients, it is a killer. Between the load and the inductance, you have a simple L-R circuit that limits di/dt.
For example, your processor may have a 1-V supply with a 10-A load, which could simply be modeled as a 1V/10A = 0.1-O resistor. If you hooked up that resistor with three inches of wire, you would add about 50 nH of series inductance. The time constant of that circuit is L/R or T = 500 ns. The expression for the current takes the following form. (The maximum rise occurs at zero and has diminished by 63 percent at one time constant.)
The maximum rise time for a 10-A current step would simply be I/T or 20 A/µs. This is a much smaller rise time than the 100 A/µs the processor guys throw around, and it highlights the need to minimize inductance.
Obviously, wirewound and physically long resistors do not make good test loads, due to their self-inductance. A good rule of thumb to estimate single-wire stray inductance is 15 nH per inch. One effective way to reduce this hookup inductance is to use multiple SMT resistors in parallel over a ground plane. To minimize interconnect inductance, you should include these load resistors on the prototype power supply board.
The figure below shows an example load test circuit that includes the load resistors, series MOSFETs, and drive circuitry. This provides two options to drive the load switch MOSFETs: a buffered drive driven by either a pulse generator or an onboard timer.