Table 3 shows the output for My_Task_1. To get an accurate distribution of the instruction type within a code structure, use a good decompiler such as Hey-Ray, Intel Vtunes or boomerang. The number of tasks or threads will differ based on the application. Getting this amount of flexible instruction sequence to simulate is hard to achieve using an ISS but fairly easy using a good software generator.
Moreover, you can run the tasks in order, random order or based on the input request. This mechanism can provide a lot more variety in terms of cache access, hit-miss ratio, bus activity and pipelines flushes. One can modify the task instruction mix and study the impact on your architecture by simply modifying the percentage table. This is quick to do and is not locked to a specific code implementation. Moreover the variety allows for a much larger level of architecture testing. If you look at the generated out for My_Task_1, you can see diversity in the instruction sequence, allowing for a much larger level of testing.
Table 3: Instruction sequence output associated with the first line of the instruction mix table
To view and simulate a model that uses this application-specific instruction mix table, go to https://www.mirabilisdesign.com/new/software/demo/Partitioning/SoC/Power_Perf.htm. Accept all security warning and the model will load up in the Web Page as