These noise sources can be the FPGA, the power supplies or the digital signals of the ADC itself. By designing a compact solution, barriers can be established between these noise sources and the analog input to reduce the noise coupled into the input network and the sensitivity of the system can be improved.
A compact solution may not be possible with high power amplifiers that can dissipate 4 W of power. With improvements to the noise performance of the system, low noise amplifiers with high linearity feeding a quiet ADC are required to maintain the desired sensitivity. Several advances in ADC design such as the new JESD204B standard have helped designers tackle design challenges that previously have limited receiver sensitivity. These advances, coupled with the new low power amplifiers, ultimately improve system noise performance.
Amplifier design challenges
Traditionally, high frequency applications used gallium arsenide (GaAs) or indium phosphide (InP) gain blocks to achieve high linearity and low noise. These gain blocks require voltages between 9-12 V which leads to 2-4 W of power dissipation per receiver channel.
Cooling the receiver board becomes a challenge and can degrade the performance of the system if left unmanaged. In battery powered or low voltage applications, traditional gain blocks may be a problem due to the high power dissipation.
Some gain blocks, also require some input or output matching circuitry that may change depending on the frequency range of interest. This reduces the total bandwidth that a single network can receive and increases the design time required to match the input network.
Additionally, the majority of these gain blocks are single ended, which is inherently imbalanced. Imbalance in any system will result in even order harmonics that need to be filtered to achieve good linearity. In many situations the second order terms may be close to the edge of the passband where the attenuation of the filter is low.
Since the second order harmonic distortion is not attenuated in these situations, the sensitivity of the receiver is reduced. By using a differential gain block to begin with, a balanced network can be designed, and second harmonic distortion is less of an issue.