# How to measure capacity versus bias voltage on MLCCs: Page 3 of 4 Fons Janssen, Principal Member of Technical Staff, Maxim Integrated explains how to measure capacity versus bias voltage on MLCCs.
DUT is 0V. The output voltage will vary when potentiometer R1 is varied. Adjust R1 until the output voltage reads 1.00V. Under these conditions, the peak voltage on C3 is around 2.35V.  The bias voltage can be modified and the output voltage will show the resultant percentage change in the capacitance. For example, if the output voltage is 0.80V, the capacitance at that particular bias voltage is 80% of the capacitance at 0V bias.

 This will only be linear when using a capacitor with constant capacitance up to 5V bias voltage (MKS, MKT, etc).

 To prevent saturation of Q2, the voltage peak on the collector (= V C3) should stay below the emitter voltage minus the emitter-collector saturation voltage, which yields to approximately 4V.

Lab Tests Confirm the Theory

The Figure 1 circuit was built on a small PCB. The first measurement was done using a random 10µF capacitor. Figure 4 and Figure 5 show the signals under 0V and 5V bias conditions, respectively. Figure 4. Measurement with V BIAS = 0V; Ch1 = V x; Ch2 = V y; Ch3 = V C3. R1 was adjusted so the voltmeter showed 1.000V. Figure 5. Measurement with V BIAS = 5V. The oscillation period has clearly decreased due to the reduced capacitance. Ch1 = V x; Ch2 = V y; Ch3 = V C3. The voltmeter reads 0.671V.

At 0V bias, potentiometer R1 was adjusted so the voltmeter showed 1.000V. At 5V bias, the voltmeter showed 0.671V, indicating that 67.1% of the capacitance remained. With an accurate counter, the total period, T, was also measured. T was 4933µs at 0V bias and 3278µs at 5V, indicating that 66.5% (= 3278µs/4933µs) of the capacitance remained. These values match very well, demonstrating that the circuit design can accurately measure the capacitance drop as a function

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