Design a cell-monitoring system to optimize accuracy, lower costs, or both: Page 7 of 10

December 02, 2013 //By Jeremy Georges
Design a cell-monitoring system to optimize accuracy, lower costs, or both
Jeremy Georges, MTS, Maxim Integrated discusses cell-measurement architectures for cell balancing and battery-measurement applications and presents example designs that meet diverse accuracy and cost requirements.
2.37MΩ are available. Always choose an actual value higher than the calculated value. This keeps the full-scale voltage of the divided signal below the 1.195V reference and avoids loss of data. With R 1 = 1MΩ and R 2 = 2.37MΩ and neglecting all other factors, the voltage-divider introduces 8.05mV of error.
 
The tolerance of the resistors introduces the second source of error. Assuming 0.1% tolerance on both resistors, a maximum error of 1.67mV is introduced through the tolerance alone. When added to the error discussed above, the total maximum error is as high as 9.73mV. The error increases significantly with increased tolerance.
 
Lastly, the voltage divider introduces error because of the need to multiply the output by the IN/OUT ratio. This error affects two areas:
  1. The errors introduced by the voltage-divider, as mentioned above, are introduced at the input to the ADC. This means that the error is included in the value output from the ADC. This value is then multiplied by the IN/OUT ratio. As such, the true error introduced at the output by the voltage-divider is the IN/OUT ratio multiplied by the sum of the imperfect resistor error value and the maximum error due to resistor tolerance.
  2. The IN/OUT multiplier also amplifies the ADC and reference errors. If the total error introduced by the ADC and reference is 1mV, the error from the ADC after the multiplier is 1mV x IN/OUT.

Note: The high value of R2 = 2.37MΩ along with the 10pF (maximum) input capacitance to the ADC forms an RC time constant that must be accounted for in the system. Waiting 5 times the RC value, or about 120µs in this example, before beginning the ADC conversion will allow the input capacitance to charge before sampling the signal.
 
The Component Selection

This architecture depends on a low-cost microcontroller like the Freescale Semiconductor K10P64M72SF1. The integrated SAR ADC offers 12-bit, single-ended conversions with

Design category: 

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