# Calculating power loss in switching MOSFETs: Page 2 of 6

Andrew Smith, Engineering Training Manager, Power Integrations, Inc. focuses on calculating power loss in switching MOSFETs.

through the device (incidentally, that is why the copper tab on a power package is typically at drain potential).

Trench MOSFETs typically exhibit relatively low on-resistance, but high parasitic capacitances between the gate, drain, and source. Other MOSFETs in the market follow a different approach, employing a lateral MOSFET architecture that places the source and the drain on top of the silicon, with current flowing horizontally across the structure. These lower-density MOSFETs combine moderate levels of on-resistance with relatively low parasitic capacitances.

In MOSFETs using either a trench or lateral architecture, there is a distinct relationship between on-resistance and capacitance. But it is important to remember that the ratio of R DS(ON) per unit area compared to capacitance per unit area is different for each, and each approach offers distinct advantages.

Since trench MOSFETs exhibit relatively low R DS(ON), designers can compensate for increased switching losses by using a larger transistor. At the same time, switching losses for a given on-resistance in a MOSFET using a lateral architecture can be less than half of those exhibited by a comparable trench MOSFET, allowing them to offset the higher conduction loss that their higher on-resistance generates.

Figure 1. Simplified AC capacitance model of a primary switch

Two factors contribute to switching loss: turn-on loss (see Figure 1 ), or the energy used to charge drain-source capacitance (also referred to as output capacitance, C oss); and crossover loss, or the energy lost during turn-on and turn-off transitions. Both of these factors play an increasingly important role in applications at lower power levels.

Power loss due to R DS(ON) is proportional to primary peak current. Discrete solutions using a trench process attempt to balance their relatively high switching losses with lower conductive losses. But at lower power levels, the maximum switching frequency is limited for designs following this approach.

Drain source capacitance (C oss) is present in all MOSFETs.

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