The Cambridge-based company develops IP for debugging and monitoring leading system-on-chip (SoC) designs with billions of transistors.
The new investors include two European ‘superangels’ from the EDA business, including Guillaume D’Eyssaultier, former general manager at Cadence Design Systems and CEO at picoChip. “Guillaume is a real testimonial – the superangels know just about everyone in the industry and know how hard the problem is to tackle,” said Rupert Baines, chief executive of UltraSoC.
The technology works on the power optimisation of the complex chip designs. “We don’t do power monitoring at the low level things like power glitches at the microsecond resolution,” said Baines. “We look at the system level performance of the sleep modes, for example, and how well the system algorithms are working with the power management unit (PMU), and we have research that shows that this can give a 10 to 15% improvement. For example, one customer assumed that a block was operating in sleep mode 80% of the time but they put our IP in and found it was operating 100% of the time at a low level so never went to sleep. They never know because they had no way of finding out,” he said.
The company also has a partnership with UK design house Moortec on power and temperature (PVT) sensors. “This means we can bring their sensors into a smart digital domain so you can do a lot of sysem level analysis building on their sensors,” said Baines. “For example for resiliance and lifetime reliability measuring in multicore devices, we can do load balancing over weeks and months to spread the electromigration so that one processor doesn’t wear out faster than the others – if you are doing automotive applications that’s essential,” he said.
The latest funding round was led by new investor Atlante Tech with Enso Ventures and Oxford Capital, who join existing investors Octopus Ventures and South East Seed Fund (FSE Group). HiSilicon