Power component designer Sarda Technologies in the US is teaming up with Asian assembly firm UTAC to use its Heterogeneous Integrated Power Stage (HIPS) in UTAC’s 3D SiP based on technology from German embedded board provider AT&S to improve the energy efficiency of data centers.
The HIPS is intended to replace silicon switches with GaAs in voltage regulators that increase switching frequency by 10 times, improve transient response by 5 times and reduce size by 80%. With these fast, small voltage regulators, it enables granular power delivery to reduce data center power consumption by 30%.
Servers, routers and communications systems require new power management technology to keep up with the growth in data consumption and mobile connectivity. But power delivery and heat removal issues constrain system performance, and each system board uses dozens of voltage regulators which consume precious board space. Designers can no longer rely solely on Moore’s Law to deliver the needed gains in energy efficiency. Leading edge processors now operate at less than one volt, which prevents designers from reducing operating voltage enough to keep power consumption constant while increasing transistor density. Instead, developers are turning to “More-than-Moore Scaling,” which heterogeneously integrates different materials and components to improve system performance-per-watt.
Small, fast voltage regulators enable granular power which reduces system power consumption through dynamic power management of each load. Miniaturizing the voltage regulators also frees up board space for more processors and memory to increase system performance. Increasing system performance-per-watt decreases the system cost-per-workload.
“UTAC’s 3D SiP enables Sarda to integrate GaAs switches, silicon driver and passive components in a compact, low-profile package that minimizes parasitics for efficient, high speed operation,” said Bob Conner, CEO and co-founder of Sarda. “UTAC’s collaboration with AT&S also provides a full turnkey supply chain assembly and test flow with much needed alignment of roadmaps as well as design rules for 3D SiP solutions with embedded chip in substrate technology.”
The ECP (embedded component packaging) technology from AT&S supports embedded devices