Or a manufacturer may require that supplies come up within a specified time relative to each other to avoid prolonged voltage differences on various supply pins. The power-on sequence between processors and external memory can also be critical.
Chip manufacturers may specify that particular supplies must come up monotonically to avoid multiple power-on resets. This can be challenging since inrush currents can place high transient demands on point of load regulators. In this case the shape of power rail startup is as important as the timing sequence. Once you combine the various chip supply requirements, bulk supplies, reference supplies and multiple point-of-load regulators for other ICs in a design, you can get up to seven or eight power rails in a hurry.
Using a 4-channel oscilloscope to verify power rail timing in an embedded system can be time-consuming, but this is how most engineers do it currently. In this article, we’ll first look at why this can be challenging with a 4-channel scope for this purpose, and then we’ll show a few examples using an 8-channel scope, which have becoming increasingly more common across the industry.