EPS efficiency challenges
The global regulatory environment for external power supply (EPS) efficiency has rapidly evolved over the past decade since the California Energy Commission implemented the first mandatory standard in 2004. While many countries still have voluntary programs, the U.S. (Energy Independence and Security Act [EISA]-2007), China (National Resources Defense Council [NRDC]) and European Union (Code of Conduct [CoC] V4) now have mandatory EPS energy-efficiency regulations. Today, Level V performance meets or exceeds the requirements of any governing body around the globe. However, the next generation of EPSs that will enter the market will be significantly different from their immediate predecessors.
The driver behind these changes is the new Department of Energy (DOE) Level VI specification , effective February 2016 and mandating compliance for all covered EPSs manufactured in or imported into the United States. At the time of its adoption, Level VI will be the toughest mandatory EPS efficiency specification anywhere in the world.
The Level VI standard will affect a wide variety of EPSs used in consumer applications and tighten their minimum average efficiency during active mode (25-100 percent load) and maximum-input power consumption during standby mode. Standby power consumption must be limited to 100 mW for ≤49-W designs and 210 mW for >50-W designs. Although the European Union CoC V5 Tier-2 EPS specifications effective January 2016 are voluntary, they do go further than the mandatory DOE Level VI specifications by requiring higher efficiency, lower standby power and additionally specify minimum efficiency requirements at 10 percent load. As shown in Figure 1, a <25-W single output low-voltage (<6-V) EPS will be required to improve average efficiency by 4 percent or higher with respect to current Level V standards – a challenging task.
Figure 1: Four-point average efficiency requirements for low-output-voltage EPSs
In a conventional diode-rectified flyback converter, the output rectifier is a substantial power-loss contributor. The average current in the rectifier is equal to the DC output current, and the peak current can be several times higher, depending on the duty cycle of the converter. The forward-voltage drop of the rectifier is typically 0.5 V for Schottky diodes, which means that in a 5-V output converter, the rectifier diode alone can result in power loss of about 10 percent. You can implement synchronous rectification (SR) to boost efficiency and reduce heat by replacing the high-loss diode rectifier with an actively controlled MOSFET. With rapid advancements in low-voltage MOSFET technology, very low on-resistance (RDSON) MOSFETs can reduce the forward drop in the rectifier to <50 mV, resulting in a tenfold improvement in losses.
The transition to SR seems imminent and inevitable for most designers trying to comply with the new regulations and ever-shrinking form factors for EPSs. However, the complexity, cost, limited compatibility with various converter operating modes and inability of existing SR controllers to extract maximum rectifier performance have in one way or another limited the wide adoption of SR. In this article, I’ll discuss the performance limitations of drain-to-source voltage (VDS) sensing-based rectifier control and how a fundamentally different control principle can enable high-performance SR in flyback converters.