# Efficiency of half-bridge vs. inverter DC/DC topologies (Part 1 of 2)

Dave Divins of International Rectifier Corp. examines switching topologies including half-bridge and inverter topologies, the end applications, and how their components and component parameters affect overall efficiency.

Switching topologies, by their very nature, are more efficient than their linear counterparts. These topologies come in various forms and their components play a significant role in the overall efficiency of the circuit. This article will illustrate the half-bridge and inverter topologies, the end applications, and how their components and component parameters affect overall efficiency.

With the advent of the electronic power switch, in particular power MOSFETs and IGBTs, switching-circuit implementation has been the topology of choice. The main reason for using switching topologies is that when you switch an input voltage with a duty cycle at high frequency, the result is an output whose average value is obtained by filtering.

The filtered switched input voltage results in the desired output voltage of the application; whether it is the output voltage of a point of load converter (POL), the inverter output of a motor drive, or the output of a Class D audio amplifier. Converting the input voltage to an output voltage using switching is significantly more efficient than using a linear amplifier/converter.

Power losses in a switching application are represented as follows ( Equation 1 ):

which  represents the total losses of a switch (i.e. MOSFET or IGBT), in a switching application.   In a given topology, there are usually one, two, four, or six switches, therefore ( Equation 2 ):

where n = number of switches in the topology.

If we compare the losses in a simple linear regulator to a switching point of load (POL) implementation we can see the obvious advantage of the POL .

Linear Regulator

Figure 1: Typical linear regulator

Equation 3 shows power loss in a linear regulator, Figure 1 .

The efficiency of this power supply can be calculated as follows ( Equation 4 ):

where ( Equation 4a ):

(Note:  This calculation does not include power loss associated with internal bias current in the

Design category: